CPU, Main Memory and the Fetch-Decode-Execute Cycle
The Von Neumann Stored-Program Concept
Every computer you have used — from a school laptop to a smartphone — runs on the same fundamental idea: both the program instructions and the data those instructions act on are stored together in the same memory. This is the von Neumann stored-program concept, named after the mathematician John von Neumann, whose work in the 1940s described this model. Before this idea took hold, changing what a computer did meant physically rewiring it. The stored-program concept meant you could change a program simply by changing the data in memory — the same hardware could run any program.
Main memory (RAM) is where instructions and data live while the computer is running. The CPU reads instructions from RAM, processes them, and writes results back. Because RAM is directly accessible by the CPU, it is far faster than any secondary storage device. However, RAM is volatile — everything in it disappears when the power is switched off.
The CPU itself has three key components: the control unit, the arithmetic logic unit (ALU) and registers. The clock times its work, and the three buses (address, data, control) connect it to memory. The CPU works directly with main memory (RAM). Every instruction the CPU executes was stored in RAM as data.
Inside the CPU: Components and Their Roles
The control unit does not process data itself. Instead, it orchestrates everything else — sending signals to tell the ALU to calculate, instructing memory to send data, and directing results to the correct destination. During the fetch-decode-execute cycle, the control unit is in charge of every stage.
The ALU is where all computation happens. Arithmetic operations include addition and subtraction. Logical operations include comparisons between values and Boolean operations. Every time a program checks a condition (is the score greater than 50?) or performs a calculation (total price × quantity), the ALU is doing the work.
Registers are tiny storage areas on the processor chip itself. Because they are physically part of the CPU, they can be accessed far faster than RAM. They hold the data that the CPU is working with right now — for example, the result of the last calculation or the address of the next instruction to fetch. You do not need to know the names of specific registers for your exam.
The clock generates a continuous stream of electrical pulses. Each pulse can trigger the start of a new stage in the fetch-decode-execute cycle. The faster the clock, the more stages the CPU can complete per second. A modern CPU typically operates at several gigahertz (GHz) — billions of pulses per second.
A bus is a collection of parallel wires. The CPU communicates with RAM (and other components) via three buses, each carrying a different type of signal:
Address bus — carries the memory address the CPU wants to read from or write to. It is one-directional: the CPU sends addresses out, but nothing sends addresses back to the CPU. The number of address lines determines how many distinct memory locations the CPU can access.
Data bus — carries the actual data or instruction being transferred. It is bidirectional: data travels from RAM to the CPU during a fetch, and from the CPU back to RAM when the CPU writes a result.
Control bus — carries control signals that coordinate the activity of all components. For example, it carries a signal telling RAM whether the current operation is a read (fetch data) or a write (store data). Without the control bus, components would not know when to act or in what direction data should flow.
Together, the three buses make up the system bus — the communication highway between the CPU and main memory.
The Fetch-Decode-Execute Cycle
The CPU operates by endlessly repeating a three-stage process for every instruction in a program. This is the fetch-decode-execute cycle. Each instruction is processed in strict sequence: fetch, then decode, then execute.
Stage 1 — Fetch: The CPU needs to know which instruction to get. It places the address of the next instruction on the address bus. RAM responds by placing the instruction on the data bus. The control bus carries a “read” signal telling RAM that this is a fetch operation, not a write. The instruction arrives at the CPU and is held in a register ready for the next stage.
Stage 2 — Decode: The control unit examines the instruction and works out what operation is required. Different instructions mean different things — one might mean “add two numbers”, another might mean “move data to a different memory location”. The control unit figures out which components need to act and what data they need. No data moves along the buses during decode; this stage happens entirely inside the CPU.
Stage 3 — Execute: The instruction is carried out. If it is an arithmetic operation, the ALU performs the calculation. If data needs to be written to RAM, the CPU places the destination address on the address bus, the data on the data bus, and sends a “write” signal on the control bus. Once execution is complete, the cycle immediately begins again for the next instruction.
This cycle repeats billions of times per second. A common exam error is writing only two stages (“fetch and execute”). There are always three stages: fetch, decode and execute. Omitting decode loses a mark.
During Fetch: the address bus carries the address; the data bus carries the instruction back; the control bus signals a read. During Decode: the control unit interprets the instruction — no bus activity needed. During Execute: the ALU or memory handles the operation; the data bus may carry a result back to RAM via a write signal on the control bus.
Putting It Together: A Worked Example
Imagine a simple program instruction: “Add the value stored at memory address 50 to the value stored at memory address 51 and store the result at address 52.”
Fetch: The address of this instruction (say, address 10) goes out on the address bus. RAM sends the instruction back on the data bus. The control bus signals “read”.
Decode: The control unit reads the instruction. It identifies this as an “add” operation needing two source addresses (50 and 51) and a destination (52). It prepares the ALU.
Execute: The CPU fetches the value at address 50 (using the address bus and data bus), then fetches the value at address 51. The ALU adds them together. The result is placed on the data bus; address 52 goes on the address bus; the control bus signals “write”. RAM stores the result. Cycle complete — on to the next instruction.