Fetch-Decode-Execute and CPU Performance

The Fetch-Decode-Execute Cycle

Every program your computer runs — from a simple calculator to a complex video game — is ultimately a list of instructions stored in memory. The Fetch-Decode-Execute (FDE) cycle is the process a CPU uses to work through those instructions, one at a time, billions of times per second. Understanding the cycle also means understanding exactly which register does what during each stage.

Stage 1 — Fetch

The cycle begins with the CPU needing to retrieve the next instruction from main memory (RAM). Here is the sequence of register operations during the fetch stage:

The Program Counter (PC) holds the address of the next instruction. This address is copied into the Memory Address Register (MAR).
The PC is immediately incremented so it points to the address of the instruction after that — ready for the following cycle.
The CPU sends the address in the MAR along the address bus to RAM. RAM returns the instruction at that address along the data bus into the Memory Data Register (MDR).
The instruction is copied from the MDR into the Current Instruction Register (CIR), where it waits to be decoded.

Key Fact

During the Fetch stage: PC holds the instruction’s address → address copied to MAR → PC increments → instruction retrieved from RAM into MDR → instruction copied to CIR.

Stage 2 — Decode

With the instruction safely in the CIR, the Decode stage begins. The Control Unit (CU) reads the instruction from the CIR and splits it into two parts: the opcode, which specifies the operation to perform (e.g. ADD, LOAD, STORE, JUMP), and the operand, which specifies the data or memory address involved.

For example, an instruction might say “ADD the value at memory address 200 to the Accumulator.” The opcode is ADD, and the operand is the address 200. The CU then prepares the appropriate circuits and control signals for the execute stage.

Stage 3 — Execute

The CU carries out the decoded instruction by sending control signals to the correct components. The exact actions depend on the instruction type:

Arithmetic or logic instruction (e.g. ADD, AND): the operand is passed to the ALU, which performs the operation and places the result in the Accumulator (ACC).
Load instruction: the operand’s address is placed in the MAR, the data is fetched from RAM into the MDR, and then copied into the ACC.
Store instruction: the value in the ACC is placed in the MDR, the target address goes into the MAR, and the data is written from the MDR to RAM.
Jump instruction: the operand (a memory address) overwrites the PC, so the next fetch stage begins at a different location in the program. This is how loops and branches work.

Once execution is complete, the cycle immediately repeats: the PC already holds the address of the next instruction, so the fetch stage begins again without any pause.

Key Fact

Three factors affect CPU performance: clock speed (more cycles per second means more instructions executed per second), number of cores (more cores allow more instruction streams to be processed simultaneously), and cache size (more cache means fewer slow RAM accesses).

CPU Performance Factor 1 — Clock Speed

Clock speed is how many FDE cycles the CPU completes every second. It is measured in hertz (Hz), but modern processors run at several gigahertz (GHz) — billions of cycles per second. A 3.5 GHz processor completes 3,500,000,000 cycles every second.

Increasing the clock speed means each instruction completes faster, so programs run more quickly. However, a higher clock speed generates more heat and uses more power. This is why processors come with cooling systems and why laptops throttle (reduce) their clock speed when they overheat.

CPU Performance Factor 2 — Number of Cores

A core is a complete processing unit with its own CU, ALU and registers. A single-core CPU can only execute one instruction stream at a time. A multi-core CPU (dual-core, quad-core, octa-core) can run multiple instruction streams in parallel.

If you have a quad-core processor, your computer can run four independent streams of instructions simultaneously — one per core. This is why modern computers run many applications at once without slowing to a crawl. However, software must be written to take advantage of multiple cores; a single-threaded program only ever uses one core, no matter how many are available.

CPU Performance Factor 3 — Cache Size

Cache is the fastest memory available to the CPU, but it is very expensive to manufacture. A larger cache means the CPU can hold more instructions and data close at hand, reducing the number of times it must wait for a RAM access. When the CPU looks for data and finds it in cache (a ‘cache hit’), it can proceed immediately. When it does not find it (a ‘cache miss’), it must stall and wait for RAM — which can take 100 or more times longer than a cache access.

Suppose the PC holds the value 100, meaning the next instruction is stored at memory address 100. Trace through the cycle:

Fetch: Address 100 is copied from PC to MAR. PC increments to 101. The instruction at address 100 is fetched from RAM via the data bus into the MDR. The instruction is copied from MDR to CIR.
Decode: The CU reads the instruction in the CIR. Suppose the opcode is ADD and the operand is 50 (meaning “add the value at address 50 to the ACC”). The CU prepares the ALU and sets up address 50 for a memory read.
Execute: Address 50 is placed in the MAR. The value at address 50 is fetched into the MDR. The ALU adds this value to the current contents of the ACC. The result is placed back in the ACC. The cycle immediately repeats from PC = 101.

This step-by-step register trace is exactly what exam questions ask you to produce in a ‘trace the FDE cycle’ question. Practice following the data through each register in order.

Doubling the number of cores does not double the speed of every program. Amdahl’s Law describes this: if 50% of a program must run sequentially (one instruction after another, with no parallelism), the maximum possible speedup from adding more cores is 2× — no matter how many cores you add.

Tasks that can be split into independent parallel chunks (e.g. rendering different sections of a 3D scene, running separate browser tabs) benefit greatly from more cores. Tasks that have strict dependencies between steps (e.g. calculating the next step in a physics simulation) benefit much less. This is why you should always qualify your answer when explaining cores as a performance factor: more cores improve performance only when the software is written to use multiple threads.