D-Type Flip-Flops, Latches and Up-Counters
Storing a Single Bit
Logic gates process information instantly — their output changes as soon as their inputs change. But digital systems also need to store information: a counter must remember its current count between clock pulses, and a memory circuit must hold data after the input is removed. The simplest storage element in digital electronics is the D-type flip-flop.
The D-Type Flip-Flop
A D-type flip-flop has two main inputs — D (data) and CLK (clock) — and two complementary outputs, Q and \(\overline{Q}\) (Q-bar). The key property is that it is rising-edge triggered: the flip-flop samples the D input only at the instant the clock signal transitions from LOW to HIGH. At all other times, changes on D have no effect.
At every rising clock edge: Q copies the value of D. Between rising edges: Q holds its stored value regardless of what D does. \(\overline{Q}\) is always the logical opposite of Q.
In symbol form, the D-type is drawn as a rectangle with D and CLK on the left, Q on the right, and \(\overline{Q}\) on the right with a small circle (bubble) to indicate inversion. The clock input is marked with a small triangle to indicate edge-triggering.
Timing Diagram for a D-Type Flip-Flop
A timing diagram shows the D, CLK, Q and \(\overline{Q}\) signals plotted against time. Reading one systematically is a core exam skill.
Consider the following sequence (read each rising clock edge left to right):
| Rising edge | D at that moment | Q after edge | Q-bar after edge |
|---|---|---|---|
| 1st | 1 | 1 | 0 |
| 2nd | 0 | 0 | 1 |
| 3rd | 0 | 0 | 1 |
| 4th | 1 | 1 | 0 |
Between any two consecutive rising edges, Q stays constant — even if D changes. This is the “latch” behaviour: the flip-flop has stored the bit from the previous rising edge and holds it until the next one.
The D-Type as a Data Latch
When a D-type flip-flop is used to hold a data bit so it can be read later, it is described as a data latch. The flip-flop “latches on” to the value of D at the rising clock edge and holds it. This is useful when a sensor produces a brief pulse that would otherwise be lost before a processor can act on it.
Binary Counters from D-Type Flip-Flops
If the \(\overline{Q}\) output of a D-type flip-flop is connected back to its own D input, the circuit divides the input clock frequency by 2. Each rising clock edge causes the flip-flop to toggle — the output alternates between 0 and 1 every clock cycle. This is a 1-bit binary up-counter.
To make a 1-bit binary counter: connect \(\overline{Q}\) back to D. Each rising clock edge causes Q to toggle. The output at Q has half the frequency of the clock input.
The 2-Bit Counter
Two D-type flip-flops connected in series form a 2-bit counter. The Q-bar output of the first flip-flop (Q0) clocks the second flip-flop. Both flip-flops have their \(\overline{Q}\) connected back to their own D input.
The result: Q0 toggles on every rising edge of the external clock (CLK). Q1 toggles when Q0 falls, which is the rising edge of Q-bar. So:
| Clock count | Q1 | Q0 | Binary value |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 |
| 2 | 1 | 0 | 2 |
| 3 | 1 | 1 | 3 |
| 4 | 0 | 0 | 0 (reset) |
The counter cycles through 0, 1, 2, 3, then resets to 0 — a modulo-4 count. This is a 2-bit binary up-counter. Q0 is the least significant bit (LSB); Q1 is the most significant bit (MSB).
A clock with a frequency of 4 Hz feeds a 2-bit counter made from two D-type flip-flops.
First flip-flop (Q0): toggles at every rising clock edge. Frequency of Q0 = \(4 / 2 = 2\) Hz.
Second flip-flop (Q1): toggles at every rising edge of Q0. Frequency of Q1 = \(2 / 2 = 1\) Hz.
The pattern: each stage divides the previous frequency by 2. If Q0 is connected to an LED, that LED flashes at 2 Hz. If Q1 is connected to an LED, it flashes at 1 Hz — half the rate of Q0’s LED. This frequency-halving at each stage is the key fact to know.
If the exam asks for the expected frequency of Q0 and Q1 from a 12 Hz clock:
Q0 = 12 / 2 = 6 Hz
Q1 = 6 / 2 = 3 Hz
A 2-bit counter timing diagram shows four waveforms stacked vertically: CLK (external clock), Q0 (fastest, half CLK frequency), Q1 (slowest, half Q0 frequency).
CLK: a square wave toggling continuously. Q0: toggles at each rising edge of CLK — its period is twice that of CLK. Q1: toggles when Q0 falls, which is the rising edge of Q-bar — its period is twice that of Q0 (four times CLK).
To check: count CLK pulses between rising edges of Q1. There should be exactly 4 CLK pulses per Q1 cycle. If you see 4, you have drawn the diagram correctly. Common error: drawing Q1 toggling on Q0’s rising edge instead of its falling edge.