Binary, BCD and Decade Counters with 7-Segment Displays
Beyond the 2-Bit Counter
The 2-bit counter in the previous lesson counts from 0 to 3 in binary. Extending to more flip-flop stages gives a longer count: 3 stages count 0–7, 4 stages count 0–15. These are general binary counters. However, humans read numbers in decimal (base 10). When the count needs to be displayed as a decimal digit, a binary-coded decimal (BCD) counter is used instead. A BCD counter counts from 0000 to 1001 in binary (0 to 9 in decimal) and then resets to 0000 automatically.
The Decade Counter
A decade counter counts ten states (0 to 9) and then resets. A 4-bit BCD counter is one kind of decade counter: it uses 4 flip-flop stages but resets after state 9 (binary 1001), skipping states 10–15. The reset is triggered automatically by internal logic: the moment the counter reaches the forbidden state above 9, a reset pulse clears all flip-flops back to 0000.
The 4017 decade counter IC, named in the specification, works differently: it does not give a BCD output. Inside, it is a Johnson counter (five flip-flops), and it decodes its ten states into ten separate outputs. The 4017 produces ten sequential HIGH outputs (one at a time) as the clock runs, cycling through outputs Q0 to Q9 in order. It is widely used as a sequencer — for example, to light LEDs one at a time in sequence or to step a relay through ten positions. Pin 15 (MR, master reset) can be connected to a logic gate to force a reset at any desired count, creating a modulo-N counter for any N from 2 to 10.
The 4017 Johnson decade counter has 10 sequential output pins (Q0–Q9). On each rising clock edge, exactly one output goes HIGH and all others stay LOW. After Q9, the sequence repeats from Q0. Connecting a logic gate from a chosen Q output to the reset pin (MR) makes the counter reset early, creating a modulo-N counter for any count from 2 to 10.
Creating a Modulo-N Counter
To make the 4017 reset after counting N states (instead of 10), connect the Q\(_{N}\) output back to the reset pin (MR) via a logic gate. For example, to create a modulo-6 counter (counting 0–5 then resetting), connect Q6 to MR. When Q6 goes HIGH, it immediately resets the counter back to 0 — Q6 appears only as a very brief reset pulse and is not a usable output state.
Students often miss this reset pulse and continue drawing the count sequence past the reset point. In a timing diagram, the reset causes an immediate return to 0 mid-sequence. The output that triggers the reset is a glitch — it goes HIGH and immediately LOW as the reset clears it.
For a 4017 with output Q\(_{N}\) wired to the reset pin (MR), the modulo is N — the counter visits states 0 through N−1 before resetting. The state at Q\(_{N}\) appears only as a fleeting glitch and does not count as a stable output.
The 7-Segment Display
A 7-segment display uses seven rectangular LED elements, labelled a through g, arranged to form the shape of a figure 8. By switching different segments on and off, the display shows decimal digits 0 to 9 and a selection of letters.
The standard segment layout (as seen from the front of the display):
| Position | Segment | Controls |
|---|---|---|
| Top horizontal | a | Top bar |
| Top-right vertical | b | Upper right side |
| Bottom-right vertical | c | Lower right side |
| Bottom horizontal | d | Bottom bar |
| Bottom-left vertical | e | Lower left side |
| Top-left vertical | f | Upper left side |
| Middle horizontal | g | Middle bar |
Digit patterns for 0–9:
| Digit | a | b | c | d | e | f | g |
|---|---|---|---|---|---|---|---|
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| 3 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| 4 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 5 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
| 6 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| 7 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| 8 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 9 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
Common-Cathode Displays
The specification requires knowledge of the common-cathode configuration. In a common-cathode display, all seven LED cathodes connect together to 0 V. Each segment lights up when its individual anode pin is taken to a HIGH logic level. This means a logic ‘1’ on any segment pin turns that segment ON.
The Decoder/Driver IC
A BCD counter produces a 4-bit binary output. A 7-segment display needs up to 7 individual signal lines. A decoder/driver IC sits between the two. It takes the 4-bit BCD count (inputs ABCD), converts it to the correct segment pattern for that digit, and provides enough current to light the LED segments. Without the decoder/driver, the low output current of a counter IC would be insufficient to drive the display LEDs.
As well as digits 0–9, the 7-segment display can show certain letters. The specification lists the displayable characters: A, C, E, F, H, I, L, O, P, S, U, b, d, h, n. Note that some characters use uppercase (A, C, E, F) while others use lowercase (b, d, h, n) because the display geometry cannot clearly distinguish both cases for those letters.
In an exam, you may be asked to identify the digit or letter shown by a given combination of lit segments, or to state which segments light for a given character. For the letter A: segments a, b, c, e, f, g are ON; d is OFF. For the letter C: segments a, d, e, f are ON; b, c, g are OFF.
One of the most common errors in counter questions is failing to spot a reset mid-sequence. Consider a 4017 with Q5 connected to MR. The counter counts: 0, 1, 2, 3, 4 and then resets to 0 immediately when it reaches 5 (because Q5 going HIGH fires the reset before Q5 can be considered a stable state).
On a timing diagram, this looks like: five complete output HIGH pulses (Q0, Q1, Q2, Q3, Q4), then a very brief glitch at Q5 as it fires the reset, then the sequence starts again from Q0. Students who do not spot the reset draw the counter continuing to Q5, Q6, Q7 — this scores zero for the sequence.
Worked rule: if Q\(_{N}\) is connected to MR, the modulo of the counter is N (not N+1). A Q5-to-MR connection makes a modulo-5 counter (states 0, 1, 2, 3, 4 — five states).