Designing Logic Systems and NAND-Only Implementations

From Problem Statement to Logic Circuit

Logic design starts with a written specification — a statement describing exactly when the output should be Logic 1. Your job is to translate that statement into a truth table, extract a Boolean expression, and select the gates to build it. This three-step pipeline is tested in nearly every exam paper and is the foundation of all digital design work.

Once you can design with standard gates, you will learn the most important conversion skill in this unit: replacing every gate in a circuit with NAND-only implementation. This matters because NAND gates are universal — any logic function can be built from them. In practice, a designer who needs only one type of IC can buy a single 4-NAND chip (such as the CMOS 4011) and implement any function without stocking multiple gate types.

Step 1 — Design from a Specification

Consider a burglar alarm that should activate (output = 1) when the door sensor (A) is 1 and the motion sensor (B) is 1, or when the panic button (C) is pressed (1). The Boolean expression is \(Q = A \cdot B + C\). The truth table has 8 rows (three inputs, \(2^3 = 8\) combinations). Rows where A=1 and B=1, or C=1, give Q=1.

The gate realisation needs an AND gate (inputs A and B) feeding into an OR gate alongside input C. This is a standard sum of products form. Most combinational logic specifications can be written as a sum of products, making the gate selection straightforward.

NAND Equivalents for Each Gate

The conversion to NAND-only is systematic. There is a known NAND equivalent for every standard gate. Learn these four equivalents and the conversion becomes mechanical:

NAND equivalents for standard logic gates

Standard gate	NAND-only equivalent	Boolean check
NOT (A)	One NAND gate with both inputs tied to A	\(\overline{A \cdot A} = \overline{A}\)
AND (A, B)	One NAND followed by a tied-input NOT-NAND on its output	\(\overline{\overline{A \cdot B}} = A \cdot B\)
OR (A, B)	NOT-NAND each input separately, then combine with a third NAND	\(\overline{\overline{A} \cdot \overline{B}} = A + B\)
NOR (A, B)	OR-equivalent (three NANDs) followed by a tied-input NOT-NAND	\(\overline{A + B}\)

The Conversion Algorithm — Three Steps

When the exam asks you to convert a circuit to NAND only, follow this exact sequence:

Step 1 — Redraw with NAND equivalents. Replace each gate in the original circuit with its NAND equivalent from the table above. The intermediate circuit will now contain only NAND gates — but it may have more gates than necessary.

Step 2 — Identify back-to-back (double inversion) pairs. Scan the circuit for any point where a NAND output connects directly into the “both-inputs-tied” (NOT-configured) NAND input. Two inversions in a row cancel out: \(\overline{\overline{X}} = X\). Mark these pairs.

Step 3 — Cancel the back-to-back pairs. Remove both back-to-back NANDs and connect the wire directly. This simplifies the circuit and reduces gate count. The resulting circuit is the minimal NAND-only implementation.

Double Inversion and De Morgan’s Theorem

Double inversion is the key simplification step. Any time a signal passes through two inverters in a row (or two tied-input NANDs), both can be removed. This is the step that students most commonly miss in the exam — they draw a correct but bloated NAND circuit with redundant gate pairs still in place.

De Morgan’s theorem states \(\overline{A} \cdot \overline{B} = \overline{A + B}\), which rearranges to show that NAND of the complements equals the OR, and \(\overline{\overline{A} \cdot \overline{B}} = A + B\), confirming the OR equivalent. You do not need to prove De Morgan in the exam — apply it to verify your NAND conversion is correct.

Logic ICs: The CMOS 4000 Series

In practice, logic gates are packaged as CMOS 4000 series ICs. Each IC package contains several identical gates sharing a power supply pin (V_DD) and a ground pin (V_SS). The 4011 contains four two-input NAND gates; the 4001 contains four two-input NOR gates. When using these ICs, unused inputs must be tied to Logic 0 or Logic 1 (not left floating) to prevent unpredictable switching.